preprints_ui: z76pk_v1
Data license: ODbL (database) & original licenses (content) · Data source: Open Science Framework
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| z76pk_v1 | A Low Latency and Resource Efficient Scalable RSA Cryptoprocessor Architecture | RSA is one of the well-known cryptography method used in asymmetric cryptosystems. But, RSA challenges on architecture, performance, power and resource consumption still can be improved. In this research, we propose a low-latency and resource-efficient scalable RSA cryptoprocessor architecture to deal with power and resource consumption issues. It is obtained using two approaches. First, optimization of Radix-4 Montgomery multiplication that yields the reduction on resource utilization and latency. Second, designing a scalable architecture based on the optimized Radix-4 Montgomery multiplication. The proposed design is verified in FPGA through simulation and image encryption application. Synthesis results show that the proposed design achieves an optimal design in respect of low-latency, resource-efficient and scalability. It only requires 227k cycles latency and consumes 13k logic gate utilization for 512-bit RSA. | 2020-05-20T14:37:30.519882 | 2020-06-08T18:49:25.921557 | 2020-06-08T18:49:05.817213 | inarxiv | 1 | accepted | 1 | 1 | https://doi.org/10.31227/osf.io/z76pk | CC-By Attribution 4.0 International | RSA; cryptography; low-latency; radix-4 Montgomery; resource-efficient | ["RSA", "cryptography", "low-latency", "radix-4 Montgomery", "resource-efficient"] | Trio Adiono; Iput Heri Kurniawan; Rachmad Vidya Wicaksana Putra | [{"id": "8j4d6", "name": "Trio Adiono", "index": 0, "orcid": null, "bibliographic": true}, {"id": "j4qnu", "name": "Iput Heri Kurniawan", "index": 1, "orcid": null, "bibliographic": true}, {"id": "2qhka", "name": "Rachmad Vidya Wicaksana Putra", "index": 2, "orcid": "0000-0001-8597-4530", "bibliographic": true}] | Trio Adiono | Engineering; Computer Engineering; Digital Circuits; Electrical and Computer Engineering; VLSI and Circuits, Embedded and Hardware Systems; Electrical and Electronics; Computer and Systems Architecture | [{"id": "59bacaae54be81032c8d35e9", "text": "Engineering"}, {"id": "59bacab354be81032c8d3692", "text": "Computer Engineering"}, {"id": "59bacab654be81032c8d3724", "text": "Digital Circuits"}, {"id": "59bacaba54be81032c8d37f4", "text": "Electrical and Computer Engineering"}, {"id": "59bacabf54be81032c8d390e", "text": "VLSI and Circuits, Embedded and Hardware Systems"}, {"id": "59bacac154be81032c8d396a", "text": "Electrical and Electronics"}, {"id": "59bacac354be81032c8d39cc", "text": "Computer and Systems Architecture"}] | https://osf.io/download/5ec540b6edc58c00d70ae143 | 0 | null | 2025-04-09T20:04:06.619209 |